The IBM ASIC design flow require cooperation between the costomer and the manufacturer's design house.

The IBM ASIC design flow require cooperation between costomer and the manufacturer's design house.

✍️ Design entry:-

              Design are entered in a hardware description language such as VHDL or verilog Schematic entry is also supported.

✍️Logic synthesis:-

              IBM logic synthesis tools are used to map the design into a gate level design in the IBM cell library.Logic synthesis also ensures that the design is appropriate for LSSD.

✍️ Simulation:-

              The design can be supported either at the functional or gate level.

✍️Floorplaning:-

               It can be used to estimate wiring capacitance,area and wiring congestion.

✍️Test structure verification:-

               This step ensure that the design satisfies a set of IBM defined rules that ensure the design - including RAM,etc-is in compliance with the requirements for LSSD.

✍️Static timing analysis:-

               This step analyzes the worst case clock speed for the implementation.

✍️Formal verification:-

               The design is checked for equivalent with a Boolean specification using efficient algorithms for solving the Boolean equivalance problem.

✍️CMOS checks:-

               This step checks fan -out,I/O,boundary scan and other low level circuit checks.

✍️ Design hand - off:-

                When the design is ready for physical design,a netlist,timing assertion data,pad placement and Floorplaning information are given to the IBM design centre.

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